1. Field of the Invention
The present invention relates in general to digital to analog converters (DAC), and in particular to power dissipation protection in power DACs.
2. Description of the Related Art
Class D audio power amplifiers (APAs) have been used for many years in systems, such as wireline telephony, where high bandwidth is not critical. More recently however, new fabrication techniques, and in particular, new techniques for fabricating power transistors, have made integrated class D APAs possible. This has extended their potential applications to lower-power, higher-bandwidth systems, including battery-powered portable music players and wireless communications devices.
One major advantage of class D amplifiers is their efficiency. Generally, an audio signal is converted into a relatively high frequency stream of pulses varying in width with the amplitude of the audio signal. This pulse width modulated (PWM) signal is used to switch a set of power output transistors between cutoff and saturation which results in efficiencies above ninety percent (90%). In contrast, the typical class AB push-pull amplifier, using output transistors whose conduction varies linearly during each half-cycle, has an efficiency of around sixty percent (60%). The increased efficiency of class D amplifiers in turn reduces power consumption and consequently lowers heat dissipation and improves battery life in portable systems.
As previously described, in a class D amplifier, efficiency is gained by switching the power devices hard between the power supply rails. The high frequency noise is then filtered with a low pass filter. Typically, the low pass filter is of the passive type, including inductive and/or capacitive reactive elements to smooth the signal. FIG. 1 illustrates, in block diagram form, a typical class D amplifier system 100. Amplifier system 100 includes class D amplifier 102 containing MOSFET switch 104 and delta-sigma (xcex94xcexa3) converter/PWM controller 106 receives a digitized audio input signal, which constitutes the signal to be amplified. The digital input signal may be high resolution, low data rate data, which may be converted to low resolution, high data rate data by delta-sigma converter portion of delta-sigma converter/PWM 106. MOSFET switch 104 may constitute a full bridge amplifier. The duty cycle of the PWM signal is proportional to the (quantized) amplitude of the audio signal. In other words, for each sample period, the relative time duration of the xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d levels of the PWM signal into MOSFET switch 106 are proportional to the quantized amplitude of the audio signal, and consequently the relative time intervals during which the output of the amplifier, ahead of LPF 110, is pulled up and pulled down is similarly proportional to the audio signal amplitude. (PWM signal generation techniques are discussed in the commonly owned U.S. Pat. No. 5,815,102 to Melanson, entitled xe2x80x9cDelta-sigma PWM DAC to Reduce Switching,xe2x80x9d incorporated herein by reference.) The amplified audio is recovered via low pass filter (LPF) 110, which provides the audio output to a load, Z. The high efficiency of class D amplifiers, and their associated pulse width modulation (PWM) driving schemes, permits relatively large amounts of audio power may be delivered by an amplifier occupying a relatively small physical footprint. Indeed, an integrated circuit class D power amplifier (including its associated signal processing and modulator) may deliver at approximately fifteen watts to an 8 ohm load, for example, a speaker for such an amplifier at a supply voltage of approximately 16 volts, and approximately fifty-eight watts for a 16 volt split supply voltage (xc2x116 volts). However, particular user applications may operate at different voltages, and with different load impedances. Consequently, it is desirable to incorporate a mechanism to limit the power that may be delivered to a load, in selected circumstances, to protect either the load, the amplifier device itself, or both. Traditional current limiting protections schemes, based, for example, on a measurement of the output current through a voltage drop across a resistor inserted in series with the load, are inefficient, and complicated to implement, because of common-mode rejection requirements. Consequently, there is a need in the art for systems and methods to protect components in power DAC systems having reduced power losses and implementation cost and space penalties.
According to the principles of the present invention, a gain control apparatus is disclosed that a gain control includes a first input operable for receiving a selected attenuation value set in response to a value of the supply voltage. The gain control is configured to receive an input signal at a second input, and generate a gain-adjusted output signal in response to the input signal. The gain value of the gain-adjusted output signal is offset by an attenuation corresponding to the selected attenuation value.
The inventive concept addresses a problem in power DAC amplifier systems, namely, protection of amplifier and system components from excessive power dissipation, or overdrive in a system that may be operated over a range of supply voltages. Conventional power DAC, switched-mode systems use internal current limiting to protect on-chip components and external current limiting to protect off-chip components, such as speakers or headphones. These increase the cost, as well as the footprint, of the system to accommodate current sensing components and circuitry associated therewith for measuring the current output by the amplifier. The gain offset by the attenuation value selected in response to the value of the supply voltage, limits the drive from the power DAC system.